I. Field of the Disclosure
The technology of the disclosure relates generally to static random access memory (SRAM), and particularly to multi-level cell (MLC) SRAM cells configured to perform multiplication operations.
II. Background
Processor-based computer systems include memory for data storage. Different types of memory exist, each possessing certain unique features. For example, static random access memory (SRAM) is a type of memory that can be employed in processor-based computer systems. SRAM can store data without the need to periodically refresh the memory, unlike dynamic random access memory (DRAM) for example. An SRAM contains a plurality of SRAM bit cells (also referred to as “bit cells”) organized in rows and columns in an SRAM data array. For any given row in an SRAM data array, each column of the SRAM data array includes an SRAM bit cell in which a single data value or bit is stored. Read and write operations are performed on a particular SRAM bit cell using read and write word lines which correspond to the SRAM bit cell row that includes the particular SRAM bit cell.
Data stored in an SRAM data array can be used for a multitude of operations. For example, artificial intelligence (AI) applications may employ SRAM data arrays to store data used for neural synapse computations. More specifically, neural synapse computations conventionally include performing a series of matrix multiplication operations, because such computations model the propagation of neurons across synapses in neural networks. Thus, data stored in an SRAM data array may correspond to matrices used as operands in such matrix multiplication operations. However, to perform matrix multiplication operations as described above, data stored in an SRAM data array must first be sensed and then provided to a separate multiplication circuit that performs the matrix multiplication operation.
For example, FIG. 1 illustrates an exemplary system 100 that employs a conventional SRAM data array 102, a sense amplifier 104, and a multiplication circuit 106 used to multiply matrix data stored in the SRAM data array 102. In particular, the SRAM data array 102 includes SRAM bit cells 108(1)(1)-108(M)(N) organized into SRAM columns 110(1)-110(N) and SRAM rows 112(1)-112(M). Data may be written to each SRAM bit cell 108(1)(1)-108(M)(N) using a corresponding write circuit 114, control circuit 116, and address decoder circuit 118. For example, data corresponding to a matrix having N columns and M rows may be written to and stored in the SRAM bit cells 108(1)(1)-108(M)(N). To perform a matrix multiplication operation on a matrix stored in the SRAM data array 102, data from each of the SRAM bit cells 108(1)(1)-108(M)(N) is first read using a pre-charge circuit 120 and the sense amplifier 104. The sensed data is then provided to an output buffer circuit 122, which stores the read data until the multiplication circuit 106 is ready to use the read data as an operand in a matrix multiplication operation. Thus, performing a matrix multiplication operation using the system 100 includes first sensing the data in the SRAM data array 102, and then performing the operation using the multiplication circuit 106, wherein each step and related circuitry consumes time, area, and power.